1. Field of the Invention
The present invention relates to an inverter circuit and a chopper type comparator circuit using the inverter circuit and, more particularly, to an inverter circuit for a semiconductor IC and a chopper type comparator circuit using the inverter circuit.
2. Description of the Related Art
A chopper type comparator often used in a conventional A/D converter is arranged, e.g., as shown in FIG. 1. Referring to FIG. 1, reference numeral 12 denotes a chopper type comparator main body, and a sample-and-hold circuit 14 of the chopper type comparator is provided adjacent to the main body 12. In the main body 12, n- and p-type field effect transistors (IG-FETs) Q.sub.1 and Q.sub.2 constituting an inverter 16, negative feedback switching transistors Q.sub.3 and Q.sub.4, and power sources V.sub.DD and V.sub.SS are connected as shown in FIG. 1. The sample-and-hold circuit 14 includes switches SW1 and SW2 to be ON- or OFF-controlled by signals .phi. and .phi., and a capacitor C. Note that reference symbol A.sub.in denotes a comparison input voltage; and V.sub.ref' a reference voltage.
Referring to FIG. 1, the switch SW1 at the A.sub.in side and the negative feedback switches Q.sub.3 and Q.sub.4 of the inverter 16 are turned on to store an electrical charge in the capacitor C. Since the input and output terminals of the inverter 16 are short-circuited, a potential at a point A is equal to a circuit threshold value V.sub.C of the inverter 16. Therefore, a charge Q stored in the capacitor C is represented by: EQU Q=(V.sub.C -A.sub.in)C (1)
Subsequently, the switch SW1 and the negative feed back switches Q.sub.3 and Q.sub.4 are turned off, and the switch SW2 at the V.sub.ref side is turned on. Since the charge amount stored in the capacitor C remains unchanged, the following equation is obtained assuming that the potential at the point A is V.sub.A : EQU Q=(V.sub.A -V.sub.ref)C (2)
From equations (1) and (2), the following equation (3) is obtained: EQU V.sub.A =V.sub.C +(V.sub.ref -A.sub.in) (3)
FIG. 2 is a graph showing input/output characteristics of a typical inverter. An intersection between a straight line V.sub.in =V.sub.out and a characteristic curve represents the threshold value V.sub.C of the inverter. As is apparent from FIG. 2, if an input voltage is shifted even slightly from V.sub.C, the shift appears in an amplified form in an output. That is, the following equations are obtained: EQU V.sub.1 '-V.sub.C =.alpha..sub.1 (V.sub.C -V.sub.1) EQU V.sub.C -V.sub.2 '=.alpha..sub.2 (V.sub.2 -V.sub.C)
where .alpha..sub.1 and .alpha..sub.2 are the amplification factors of the inverter 16.
According to equation (3), therefore, if A.sub.in is lower than V.sub.ref' an output V.sub.A1 (=V.sub.out) from the comparator is given by: EQU V.sub.A1 =V.sub.C +.alpha..sub.1 (V.sub.ref -A.sub.in) (4) EQU for .alpha..sub.1 &gt;1
If A.sub.in is higher than V.sub.ref' an output V.sub.A2 (=V.sub.out) from the comparator is given by: EQU V.sub.A2 =V.sub.C +.alpha..sub.2 (V.sub.ref -A.sub.in) (5) EQU for .alpha..sub.2 &gt;1
A conventional comparator circuit has a problem of offset caused by a power source resistance. That is, the input terminal of the inverter 16 is at an intermediate level upon sampling (i.e., when all of the switches SW1, Q.sub.3' and Q.sub.4 are turned on to store an electrical charge in the capacitor C). Therefore, both the p- and n-type transistors Q.sub.2 and Q.sub.1 in the inverter 16 are turned on to flow through current between the power sources V.sub.DD and V.sub.SS. Assuming that the through current is I.sub.p and power source resistances of the inverter 16 at the reference power source side (V.sub.SS side) and the supply power source side (V.sub.DD side) are R.sub.S and R.sub.D' respectively, a potential at the V.sub.SS side rises from the ground level toward the positive side by I.sub.P R.sub.S' and that at the V.sub.DD side falls by I.sub.P R.sub.D. In this case, the circuit threshold value V.sub.C is obtained as: ##EQU2## (where V.sub.TN and V.sub.TP are the threshold voltages of the n- and p-type transistors, L.sub.N and W.sub.N are the length and the width of the n-type transistor, L.sub.P and W.sub.P are the length and the width of the p-type transistor, .mu..sub.N and .mu..sub.P are the mobilities of electrons and holes, and .epsilon..sub.OX and t.sub.OX are the dielectric constant and the thickness of a gate oxide film.)
When a comparison period (in which only the switch SW2 is turned on, i.e., a state opposite to the sampling state described above) starts, the input potential of the inverter changes from V.sub.C. Therefore, the through current changes to I.sub.P '. In this case, the circuit threshold value V.sub.C ' is obtained as. ##EQU3## That is, V.sub.C and V.sub.C ' satisfy the following relation: ##EQU4##
Therefore, a charge Q' stored in the actual capacitor C upon sampling is given by: EQU Q'=(V.sub.C +.DELTA.V-A.sub.in)C
From the above equation, the potential V.sub.A at the point A upon comparison is represented as follows: EQU V.sub.A =V.sub.C +(V.sub.ref -A.sub.in)+.DELTA.V (8)
From comparison between equations (3) and (7), an offset .DELTA.V is produced in the prior art.
In order to reduce the offset caused by a power source resistance, efforts have been conventionally made to decrease the value of the power source resistance to be as low as possible. As a result, the thickness of a power source line is increased to increase the size of a chip. In addition, since the resistance is decreased to be as low as possible, the mounting position of a comparator is limited.
A conventional chopper type comparator is used in a single analog chip such as an A/D converter and is not used together with a large-scale digital circuit. In addition, a conventional chopper type comparator has no sufficient countermeasure against noise produced in a digital circuit.
An influence of noise on a chopper type comparator will be described below. A sampling period ends at an opening timing of the self-bias switches Q.sub.3 and Q.sub.4 of the inverter 16. If, however, noise is superposed on the power source to vary the circuit threshold value V.sub.C of the inverter 16 from V.sub.C to V.sub.C +.DELTA.V immediately before the switches Q.sub.3 and Q.sub.4 are opened, a charge amount Q" to be stored in the capacitor C is given by: EQU Q"=C(V.sub.C -(A.sub.in -.DELTA.V.sub.C))
and a value A.sub.in ' represented by the following equation is assumed to be input: EQU A'.sub.in =A.sub.in -.DELTA.V.sub.C
Even if the switches Q.sub.3 and Q.sub.4 are opened in this state to eliminate an influence of the noise and the circuit threshold value of the inverter 16 returns to V.sub.C' the charge amount of the capacitor C is still subjected to the influence of the noise, and the input voltage is offset by -.DELTA.V.sub.C and compared.
In a digital LSI chip such as an MPU (Micro Processor Unit) or an MCU (Micro Control Unit), it is well known that the power source noise described above is produced upon switching of an external bus buffer for driving a peripheral IC of an external bus of a digital LSI chip.
When a chopper type comparator is used in a single analog chip, switching of the external bus buffer is performed after the comparison period described above is finished. That is, since switching is not performed in the sampling period, it is not affected by the above noise. When a chopper type comparator is used together with a digital circuit such as a microcomputer, however, digital noise (external bus buffer switching noise) may be produced regardless of a sampling period and a comparison period since a digital portion and an analog portion operate independently of each other. As a result, precision of the comparator may be degraded.
As an attempt to eliminate an influence of the above noise or to reduce the noise to be negligible, an arrangement in which an analog clock is formed such that its phase is shifted from that of a digital clock is described in K. Nagai, "A Signal Processor for Voiceband Applications", ISSCC DIGEST OF TECHNICAL PAPERS; PP. 60-61, Feb., 1988. The arrangement of this reference, however, is not so preferable since
(i) an exclusive circuit for forming an analog clock is required, PA1 (ii) an RF source oscillation clock is required, and PA1 (iii) when an analog circuit is mounted together with a digital circuit, it is generally difficult to perfectly offset synchronization of circuit operations in timing design because an operation frequency margin must be considered.